Information Technology : Hardware

Information Technology Portfolios


Virtual Touch Screens: New Input for Smaller Devices

UW–Madison researchers have developed a new virtual touch screen technology utilizing unused space to the side of a device display. The technology is a low-cost passive finger localization system based on visible light sensing. It provides a simple and convenient interface that does not require additional external equipment such as a sensor attached to the finger.

A sensor system on the edge of a mobile device uses photodetectors and a light source to track finger motion based on reflected light signals within the narrow light-sensing plane of the virtual touch screen. The signals are converted to orthogonal coordinates and subsequently output to the graphics display screen.

Optimized Nanoresonator Design Signals Breakthroughs in Spectrometry and Device Efficiency

UW–Madison researchers have developed a new method and structure for increasing the cross section of nanoresonators, thereby improving the concentration ratio of light (or other electromagnetic radiation) and device performance. The key to their approach is that the nanoresonator is surrounded by a material that provides increased light concentration.

Improving Memory Access in Asymmetric Memories

UW–Madison researchers have developed a shared row buffer system for asymmetric memory. The system better accommodates changing patterns of data by sharing row buffers between fast and slow memory banks.

In general, the row buffers provide a vehicle for swapping data. They can be loaded from one memory bank and then reassigned to the other memory bank. The system provides a lightweight method of moving data between memory banks without incapacitating the memory channel or involving the processor.

Hardware Blends Compute/Storage Capabilities, Increases Efficiency

A UW–Madison researcher has developed a versatile new computer architecture using interconnected tiles that can alternate between memory and computation functions. More specifically, each tile can be configured as a (i) multibit nonvolatile memory, (ii) logic gate array or (iii) routing switch. The ability to dynamically change the function of any of the tiles allows precise tailoring to workload and reduces data transfer costs.

Phased-Array Antenna Concept Reduces Cost, Improves Power Handling

UW–Madison researchers have developed a new concept for designing low-complexity, low-cost phased-array antennas. The design consists of a collimating surface, a feed antenna and a macro electromechanical system (MaEMS) used to dynamically change the properties of the collimating surface. This surface can act in the transmitting mode (a lens) or in the reflecting mode (a reflectarray).

The researchers have explored several MaEMS tuning mechanisms to dynamically change the phase shift gradient and control the direction of the main beam of the antenna. Very small mechanical movements help achieve this tenability and the entire process can be performed extremely rapidly. Most existing solutions try to tune the capacitors.

Bringing Quantum Computers Closer to Reality by Solving Decoherence Problem

UW–Madison researchers have developed a system and method for reducing noise from magnetically active surface defects, a dominant contributor to decoherence in superconducting quantum circuits.

The researchers found that adsorbed molecular oxygen represents a major source of magnetic noise. As a result, they have developed approaches to hermetically package qubit samples in an improved vacuum environment. The developed hermetic sample enclosure prevents the adsorption of a high density of magnetically active defects on the surface of the device during cooldown. The surfaces of encapsulated devices show greatly reduced levels of magnetic activity and low-frequency magnetic flux noise.

Other tactics for reducing noise may be employed as well, such as passivating the device surface with a high density of non-magnetic adsorbates, coating the circuits with a protective non-magnetic layer or irradiating the device with ultraviolet light to drive off magnetically active adsorbates.

Managing Memory in Virtualized Computer Systems

UW–Madison researchers have developed a so-called compound page table system that blends features of shadow paging and nested paging to improve efficiency. Memory regions with stable address mapping (e.g., holding program code) may be treated using shadow paging while regions with dynamic address mapping (e.g., variable storage) may be treated using nested paging. Thus, the benefits of both techniques can be obtained.

More Efficient Signal Processing for Digital and Smartphone Cameras

A UW–Madison researcher has developed ISP circuitry than can operate in two modes. One mode optimizes the signal for human vision and the other mode optimizes the signal for feature/gesture recognition. The latter mode uses less energy because the image can be of lower quality.

The new ISP design conserves power by not processing each pixel value, operating all processing stages or sampling every frame.

Qubit Measurement System Is Efficient, Scalable

UW–Madison researchers have developed a novel qubit measurement system based on counting microwave photons. The new system replaces currently used amplification and heterodyne detection techniques.

The measurement proceeds in three stages. First, the state of the qubit is mapped to the microwave photon occupation of a readout cavity. The occupation of the cavity is subsequently detected using the Josephson photomultiplier (JPM), a microwave-frequency photon counter. The measurement leads to a binary digital output: ‘click’ or ‘no click.’ The output may be transmitted to a single flux quantum (SFQ) circuit for classical processing.

SFQ circuits, like qubit circuits, are based on superconducting thin films. Therefore, the SFQ processor could be operated on the same cryogenic stage as the quantum circuit to make the system more compact and to reduce measurement latency. Other methods rely on wiring and electrical connections to take measurements and feed them to a room-temperature device for processing, resulting in losses and inefficiencies.

New 2-D Optical Trap Array for Quantum Computing, Sensors

UW–Madison researchers have developed a new approach for trapping and controlling atomic particles using projected light. Specifically, the new method generates optically induced traps that are more effective and efficient.

The projected light fields may include linear segments of light arranged on a two-dimensional planar grid, which can be used to form optical trap arrays that define the locations of the atomic particles in three dimensions. This configuration helps arrange the atoms in individual and optically defined sites.

Memory Controller for Heterogeneous Processors

UW–Madison researchers have developed a memory controller providing improved access to common memory when a single parallel application is divided between different processor types, e.g., a CPU and a GPU. In these instances, fairness may not be a primary consideration and performance can be evaluated in terms of completing the entire application.

The controller works by dynamically adjusting access priorities between the different processors. It can predict sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences.

Voltage Regulator Control for Processors Conserves Energy

A UW–Madison researcher has developed an improved VR system for next-generation hardware providing direct rather than inferred current measurements. In the new system, a controller manages the number of active phases of each VR according to a determined electrical current demand from the processor.

Relying on electrical current demand (rather than P-state) boosts VR efficiency, particularly in situations where low current demand occurs under heavy processor demand because of certain power variations.

Memory Processing Unit Boosts Performance, Cuts Energy Usage

UW–Madison researchers have developed a system to dramatically improve the benefits of 3-D die-stacking memory. Their system allows a host processor to efficiently offload entire pieces of computation for faster processing with reduced power consumption.

More specifically, memory processing unit cores are tightly coupled with sections of stacked memory layers, combined as memory ‘vaults’ in hardware. Application code is segmented into discrete partitions (‘shards’) in software for storage in the vaults. As a result, an application program is effectively broken up for execution among multiple processing cores in close proximity to memory.

New Hardware Helps Cell Phones, Tablets Save Power

UW–Madison researchers have developed a more energy-efficient multiplier circuit for portable electronics. The circuit performs ‘dynamic truncation,’ reducing the size of operands to capture their most important bits. This allows multiplication to be performed using a much smaller multiplier, significantly reducing energy consumption.

Dynamic truncation works by preserving computationally important bits and providing approximations that are satisfactory for most applications.

More Accurate Branch Predictor Circuit

UW–Madison researchers have developed a more accurate branch prediction method by distinguishing between ‘biased’ and ‘non-biased’ branch instructions. Biased branches are consistently skewed towards one direction while non-biased branches resolve in both directions.

The new method filters out biased branches because they merely reinforce earlier prediction decisions. Favoring non-biased branches enables more far apart correlations and superior prediction accuracy.

Controlling Superconducting Quantum Circuits

UW–Madison researchers have developed a method for controlling superconducting quantum circuits. In the new method, quantized voltage pulses generated by SFQ circuits are used to coherently control superconducting quantum systems, such as qubits or resonator cavities.

More specifically, the method utilizes coherent rotations obtained using a pulse-to-pulse spacing timed to the period of the target oscillator. Controlling the system in this way may be achieved in a low-temperature cryostat without the need to apply external microwave electromagnetic signals. Also, the SFQ-based gates are robust against leakage errors and timing jitter, with high fidelities achievable for gate times on the order of tens of nanoseconds.

Ultrawide Band, Low-Profile ‘Stacked’ Antenna System

UW–Madison researchers have developed a compact, ultrawide band antenna system with monopole-like radiation characteristics and a bandwidth of 10:1. The system is designed with two antennas wherein one is a scaled-down version of the other. The two antennas can ‘stack’ or ‘nest’ to be less conspicuous. A feed network feeds the appropriate antenna based on the frequency of the input signal. This enables the design to work as a single, ultrawide band system.

Increasing Memory Bandwidth

UW–Madison researchers have developed a system to substantially increase memory bus bandwidth by combining a parallel memory bus with a high-speed serial memory bus. A serial memory bus normally introduces too much latency (data delay) for general computer processors, but this can be accommodated using special processors like GPUs or streaming processors.

By selectively steering some memory traffic to the serial memory bus, total memory bandwidth is significantly increased while still providing low latency when needed via the parallel memory bus.

Computer Accelerator System Boosts Efficiency

UW–Madison researchers have developed a specialized memory access processor that takes over the job of feeding data to the accelerator. It is placed between the main processor and the accelerator.

The circuit is specialized for a narrow task, in this case performing memory access and address calculations. It is as fast as the main OOO processor yet more efficient. The main OOO processor – free from memory access duties – may switch to an energy conserving sleep mode until the accelerator is finished, or may move on to other tasks.

Improved Gate Design for Quantum Computers

UW–Madison researchers have developed quantum dots with a novel tunnel barrier gate design. The structure consists of a quantum well layer with three 2DEG regions separated by three tunnel barriers.

An electrode is patterned on a dielectric layer (instead of directly on the dot surface) above the first tunnel barrier. The various electrodes formed on the dielectric layer are arranged to define quantum dot regions within which the energy level and spin of electrons can be manipulated.

The multiple layers of the structure can be made using conventional deposition systems or lithography techniques.

Managing Computer Power and Performance

UW–Madison researchers have developed a set of predictors to monitor the energy consumption and performance of a computer’s individual components in runtime. This information can be used to manage the system based on user needs (i.e., higher power/higher performance; reduced power/reduced performance).

The predictors work by establishing predicted tradeoffs between power and performance for a particular workload while it is being executed. The predictions are combined in a system model to identify a limited number of operating state combinations. This allows operating states to be readily adapted during program execution based on a particular workload. Pareto optimal settings can be used to simplify adjustment of the system during runtime.

More Efficient Processing with Self-Invalidating IOMMU Mapping

UW–Madison researchers have developed a more efficient IOMMU. They recognized that the time required to delete a page table entry (PTE) from the page table and send the IOMMU cache deletion signal can be eliminated for most transactions.

This is done by attaching a ‘removal rule’ to the PTE that allows for self-deletion. The removal rule may, for example, delete the PTE after a predetermined number of memory accesses or a specified time. This significantly cuts processor time and resources required for IOMMU transactions. Also, the susceptibility of the computer to I/O device or driver errors is reduced.

Predicting Logic Gate Failure

UW–Madison researchers have developed a new fault prediction technique providing accuracy, generality and power efficiency. To do this, two similar circuit modules are used but one is artificially aged. Aging can be mimicked by lowering operating voltage and/or phasing a sampling clock to reduce slack time. Both approaches make the ‘aged’ gate more sensitive to delay. To achieve power efficiency, a novel technique is used to turn on this ‘mode’ at a low periodic rate.

The outputs of the two circuit modules is compared. Discrepancy in output indicates a projected failure.

Maximizing Multicore Processor Performance

A UW–Madison researcher has developed a solution for improving performance while still meeting a maximum power budget for multicore processors operating in a power-constrained environment.

The method provides for joint scaling of both the number of cores in operation as well as the amount of resources per core. Selecting the number of cores and the amount of resources is done by examining the degree of ILP and TLP available for a given application. As such, performance counters (and other characteristics) implemented by a processor are used to determine optimal core/resource configurations.

Performance counters may measure, for example, how many instructions are executed per cycle, length of execution time and cache hit rate. These performance measurements indicate how much ILP and TLP a given application exhibits at a time.

Ultra-Efficient Continuous Monitoring of Sensors

UW–Madison researchers have developed reconfigurable event-driven hardware that enables low-power continuous monitoring by offloading tasks from the primary processor.

The hardware interfaces with sensors and invokes the processor only when a trigger signature is detected. It can be implemented as a separate integrated chip or as a low-power compute resource within the primary processor.

SuperTag Cache for Energy-Optimized Compression

UW–Madison researchers have developed a compressed cache, called SuperTag, which exploits spatial locality to optimize compression effectiveness and energy use.

SuperTag cache manages cache at three granularities: ‘super blocks,’ single blocks and fractional data segments. Since contiguous blocks have the same tag address, SuperTag increases per-block tag space by tracking super blocks (for example, a group of four aligned contiguous blocks of 64 bytes each). It also breaks each cache block into smaller data segments for storage.

To improve compression ratio, the technique uses a variable-packing scheme allowing variable-size compression blocks without costly compaction. It also co-compresses contiguous blocks, including within the same super block, thereby producing data segments for storage.

LEAP - Improved Data Lookup for High-Speed Routers

UW–Madison researchers have developed LEAP (Latency, Energy and Area Optimized Lookup Pipeline), an improved tile-based approach for routing data packets in a network.

The router has a series of ports for receiving and transmitting packets, and communicating with a general-purpose processor. The router’s packet processing engine receives data and conducts memory lookups. The engine includes a set of connected computational tiles. Each tile has a set of functional units with inputs and outputs for processing arguments, and a store for holding instructions. Also, the tiles have a programmable multiway switch for communicating with the functional units and act according to the stored instructions.

The functional units may access a lookup memory holding packet data while interconnection circuitry manages communication of data between tiles.

More Efficient, Portable Graphic Processing System by Exception Handling

UW–Madison researchers have developed a method for GPU exception handling that overcomes the problem of state storage by identifying idempotent regions of the executed code. Idempotence describes an operation that produces the same results if executed once or multiple times, meaning it can be retried as often as necessary without causing unintended effects. Identifying these regions allows a state to be restored (without storage) by simply moving backward in the program.

The method decomposes GPU programs into idempotent sequences and regions. GPU programs tend to have very large regions of code that are idempotent. They can be used to rapidly service infrequent exceptions and those, like page faults, that require a context switch. For data mis-speculations, regions can be further divided into fast idempotent sub-regions. Additionally, a compiler incorporated into the GPU architecture reviews instructions to identify idempotent regions and mark those readable by the GPU.

Low-Noise, Phase-Insensitive Linear Amplification at Microwave Frequencies

UW–Madison researchers have developed a system and method for a low-noise, phase-insensitive linear amplifier capable of accommodating readout signals from quantum computing applications, even when such signals reach frequencies in the RF and microwave range. The amplifier can improve signal-to-noise ratio significantly by incorporating a low-inductance device geometry that is compact, straightforward to model at microwave frequencies and readily integrated into an RF or microwave transmission line environment. The device’s input and output can be matched to transmission-line impedances.

The amplifier system includes an input providing a direct coupling configured to receive a high-frequency input signal. The system also includes an amplifier containing a dielectric material separating superconducting layers, forming an amplifier loop configured to receive the input signal and deliver an amplified signal. The system includes an output providing a direct coupling configured to deliver the amplified signal. A quantum information processing network is configured to receive and relay high-frequency signals. The network includes a signal source, a source of qubits and a linear cavity resonator. The network also includes a transmission line communication system configured to transmit and receive the high-frequency signal, and an amplifier coupled directly to the transmission line communication system through an input and output.

Dual-Loop Cooling System for Electronics

A UW–Madison researcher has developed a dual-loop, refrigeration-based cooling system for thermal management. This system improves the efficiency of spray cooling technologies by controlling the temperature and pressures within the system in a more accurate way than in traditional systems.

The system contains two loops, rather than one loop in series, which separates refrigeration from thermal management. The key is that the liquid leaving the pump is cold and at relatively high pressure, so that once expanded through the nozzles, the fluid will be liquid. This is ideal for two-phase impinging jets. However, for a spray cooling system, the liquid needs to be at a specific saturation condition before entering the nozzles so vapor will be generated. To achieve this, the liquid leaving the pump needs to be heated. This can be done with a heat exchanger and a second stream of warm fluid using a vapor mixer, which is found in the new loop in the system. A detector also is added to help identify when the saturation condition is met.

Computer Architecture Enables Simplified Recovery from Speculative Execution Errors without Checkpoints

UW–Madison researchers have developed a simplified processor that can recover from mis-speculation or execution of other erroneous instructions without maintaining or reloading a conventional checkpoint. The processor simply re-executes from the start of a block of instructions that includes the erroneous instructions. This is possible by constructing programs in terms of consecutive idempotent regions, which produce the same results even when executed repeatedly, and limiting speculation to occur in those regions. The ability to recognize (at compile-time) and exploit idempotent regions eliminates much of the circuitry and energy consumption needed to recover from mis-speculation or hardware failure.

Design of Keyboard for Improved Accessibility to Electronics

UW-Madison researchers have developed an extension to the EZ Access set of design guidelines, techniques and hardware components. Compact EZ Access keys and functionality can be incorporated into existing or new public information and transaction machines to provide both standard and special keyboard behaviors needed by people with different disabilities. The system incorporates the EZ UP and DOWN, EZ ACTION, EZ BACK and NEXT and EZ HELP buttons of the original EZ Access system into a typical keyboard to improve accessibility of the system and add convenience to users without disabilities. These buttons enhance the functionality of the original arrow and enter keys of a keyboard to allow easy navigation by page, screen or element, while maintaining typical functionalities such as moving the text cursor and typing carriage returns. The first figure below shows the intended design of the EZ Access buttons. These buttons can be arranged in different configurations to meet the needs of the machine or electronic device being modified.

Pipelined Lookup Grid Architecture (PLUG)–Fast, Cool and Flexible Network Processing

UW-Madison researchers have developed Pipelined LookUp Grid (PLUG) as a component that can accommodate many types of lookup operations performed by network equipment while processing traffic.  PLUGs offer a hybrid of storage and computation functions to address the energy efficiency and performance requirements of network devices.

PLUGs provide a specialized circuit for performing lookup operations in which the memory of a lookup table is divided into “tiles.”  The connections between these tiles may be flexibly changed to match the particular problem being addressed.  When a tree-type lookup is preferred, such as with IP addresses, the tiles can be configured into a tree structure.  Conversely, when a hash table is preferred, such as in Ethernet-type lookups, the tiles can be reconfigured in parallel ranks suitable for hash tables.  The ability to programmably configure individual memory elements allows the router to flexibly move between protocols and to manage lookup decisions at a phenomenally high rate (1 to 1.5 billion decisions per second).

Signature-Based Transactional Memory for Improved Performance of Multiple Thread Microprocessors

UW–Madison researchers have developed an HTM system that summarizes read- and write-sets in “signatures” for conflict detection without coupling conflict detection and version management together in memory caches. The transaction updates memory in the cache or memory, while saving the old value in a memory log for the specific thread. After each transaction, the transaction signature is cleared. These signatures can be used without requiring modifications to latency-sensitive structures such as the memory caches. Combining multiprocessor TM signatures and logs and with high performance multiple processor microprocessors improves the ability for operating systems and virtual machine monitors to virtualize transactions.

Thin-Film Semiconductor for Increasing Microprocessor Speeds

UW-Madison researchers have developed a method for fabricating a heterogeneous semiconductor structure that enhances both electron and hole mobility. This method extends a previous patent (see WARF reference number P06047US) to allow the fabrication of mixed-crystal-orientation silicon that incorporates the hole mobility enhancing strained Si(110) with the high electron mobility of Si(001).

During fabrication, a thin, single-crystal silicon membrane with regularly patterned holes is applied on a silicon substrate with a different composition, orientation or strain state. The holes then are filled by growing up the bottom layer. Alternatively, the bottom silicon semiconductor layer is patterned with regularly spaced holes. Then a second single-crystal membrane with a different composition, orientation or strain state is applied as a layer over the first and fills the holes. When the top is smoothed, islands of the second layer remain, surrounded by the first. The difference in crystalline orientation, semiconductor composition and/or degree of strain between the silicon layers results in one type of silicon experiencing enhanced electron mobility while the other experiences enhanced hole mobility.

Over-Provisioned Multicore Processor Computing System

UW-Madison researchers have developed an over-provisioned multicore processor system (OPMS) that integrates more processing cores than would normally be allowed by the power budget. The system does not increase the number of cores running at a given time, but rather keeps them in variable states of activity and quiescence, and flexibly assigns computation onto processing cores.

The invention spreads the computational load over the additional cores, and enables several techniques to improve system performance and energy efficiency. In particular, an OPMS can enable both static and dynamic heterogeneity, where different processing elements are assigned tasks to which they are best suited, thereby improving power-performance for a range of applications. The invention includes a controller for the cores that may be implemented in firmware, software and/or circuitry.

Domino Logic Circuits Capable of Reducing Power Consumption by Controlling Leakage

UW-Madison researchers have developed new circuit topologies for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and dual threshold voltage complementary metal oxide semiconductor (CMOS) technology are used to place idle domino logic circuits into a low leakage state. Sleep transistors added to the dynamic nodes reduce the subthreshold leakage current by turning off at least some of the high threshold voltage transistors. Sleep switches are added to the output nodes to suppress the voltages across the gate, thus insulating layers of the transistors in the fan-out gates and minimizing the gate tunneling current.

Low Swing Domino Logic Circuits Reduce Power Consumption in High-Performance Microprocessors

UW-Madison researchers have developed improved low-voltage swing techniques for simultaneously reducing the active and standby mode power consumption and enhancing the immunity to noise in domino logic circuits. One circuit technique modifies the upper and lower boundaries of the voltage swing at the dynamic node while maintaining full voltage swing signals at the inputs and outputs. The circuits may utilize two power supplies and/or two ground voltages. Other circuit topologies include dynamic node low voltage swing circuits, a domino circuit with modified output voltage swing to reduce dynamic switching power consumption, multiple threshold voltage implementation of low swing domino logic circuits for suppressing the subthreshold leakage current, body-biased embodiments of low swing circuits and dynamic node low voltage swing circuits with single power supply or ground voltage.

High Performance Amplifiers for Better Wireless Communication

UW–Madison researchers have developed a new amplifier design that will enable the production of high power/high frequency wireless devices. In the new design, emitter fingers are arranged such that heat dissipates more smoothly and the device can operate at a uniform low-junction temperature.

More specifically, the emitter fingers are made up of subcells. They are configured in a one- or two-dimensional form having a hollow center layout, where some of the fingers or subcells are left out during design or disconnected during manufacturing. They also may be arranged in arc-shaped rows. Both configurations prevent hotspots from forming and maintain thermal stability at high power.

Multi-Mode Liquid Cooling System for Electronics, Including Computers

By mixing together liquid coolants of different volatilities and boiling points, UW-Madison researchers have devised a means to efficiently remove heat from electronics, while avoiding potentially damaging dry-out conditions. In this system, a more volatile coolant of lower boiling point begins to evaporate as it flows over the hot surface. This phase change from liquid to vapor removes heat much more efficiently than can be achieved through simple heating of the liquid. At the same time, a less volatile component in the mixture remains liquid. This keeps the surfaces of electronic circuitry wet at all times, preventing dry-out and associated temperature fluctuations.

Adaptive Cache Compression System

UW-Madison researchers have developed a flexible cache compression system that dynamically adapts to the costs and benefits of compression. Data in a cache are selectively compressed based on predictions as to whether the benefit of compression in reducing cache misses exceeds the cost of decompressing the compressed data. The predictions are based on an assessment of actual costs and benefits for previous instruction cycles of the same program.

Scalable Monitor of Malicious Network Traffic

The researchers have now developed an improved, scalable device that attaches to unused addresses and monitors communications to detect malicious network traffic. The device includes an active responder that simulates communication by an actual computer, but which requires fewer processing resources and may be readily scaled to monitor large numbers of network addresses. Preferably, the active responder provides a response based only on the previous statement from the malicious source. In most cases, this is sufficient to promote additional communication with the malicious source, presenting a complete record of the transaction for analysis and possible signature extraction. Experiments in a controlled laboratory situation as well as in a case study showed this device is efficient, scalable and useful.

Full Coverage Spray and Drainage System for Orientation-independent Removal of High Heat Flux

UW-Madison researchers have developed an improved spray cooling system and method for cooling electronic circuitry in high-performance computers and other similar systems. The method involves directing a spray of cooling fluid onto the surface of a chip at an angle. The cooling fluid then flows in one direction along the circuitry toward the drainage point(s). Directing the spray along the chip with high momentum allows the system to be portable, because a uniform layer of coolant is maintained even when the orientation of the system varies. The cooling fluid is efficiently delivered by several fan-shaped sprays that are positioned to cover the entire heated surface without allowing interaction between the spray plumes that could otherwise lead to coolant buildup and poor heat transfer.

SISO Model Predictive Controller

UW-Madison researchers have developed a fast, easily tuned controller specifically tailored to SISO processes. The controller combines the best features of model-based control methods and PID controllers and performs better than PID controllers on all SISO processes.

This offset-free, constrained, linear quadratic (CLQ) controller has three modules: a state and disturbance estimator, a target calculation and a constrained dynamic optimization. Each of the modules is implemented efficiently so that the overall CLQ algorithm has little computational cost and can be applied using simple hardware and software.

Spin Readout and Initialization in Semiconductor Quantum Dots

UW-Madison researchers have now developed a semiconductor-based, quantum dot scheme for enabling measurement of the spin states of individual qubits without the need for additional external couplings that can cause decoherence. In this quantum dot scheme, the energy levels of trapped qubits are controlled by varying the voltages of nearby metal gates. By bringing specific energy levels into resonance with an applied microwave field, the qubits can be made to undergo spin-dependent oscillations that are detected by a single electron transistor.

Solid-State Quantum Dot Devices for Quantum Computing

An interdisciplinary team of UW-Madison physicists, engineers and materials scientists has now designed a scalable, multilayer semiconductor device that can be used to build a quantum computer. Fabricated by growing layers of semiconductors and patterning electrostatic gates on the surface, this quantum dot device traps individual electrons in a solid, brings the electrons close to each other, maintains the electrons’ phase coherence and allows manipulation of the electrons’ individual spin states.

Smarter Cache Memory by Dynamic Sub-Block Data Fetching

UW–Madison researchers have developed a cache structure that dynamically changes the fetch block size by considering the historical success of previous sizes in satisfying processor requests. Moreover, the blocks may include data from discontinuous address ranges.

Specifically, the cache is divided into blocks, each holding data from an address range of the memory, and further divided into sub-blocks. A use table has entries indicating the sub-blocks that have had their data used by the processor since the block was loaded. Based on this information, a fetch size controller provides a size value for a given data address range. ‘Miss processing circuitry’ responds to processor requests by loading the specified data into a number of sub-blocks of the cache block determined by the fetch size value for that address range.

Faster Data Mining by Subset Binary Decision Trees

UW–Madison researchers have developed a new method of data mining using a low-access memory to store records and attributes, as well as a smaller, high-speed memory that will estimate a final classification scheme from a sequence of partial decision trees.

First, a subset of the database is loaded into the smaller memory to prepare partial trees associated with different attributes. These are combined to form an initial tree representing a statistically good estimate of data patterns. This estimate is used then to review the entire database in a single scan to verify and refine a final structure.

Memory Bypass Circuit for Faster Data Transfer

UW–Madison researchers have developed a technique for predicting data dependence that can be used to establish a link between two instructions. Accessing the data from standard or cache memory may be bypassed.

In its place, the data retrieved in the first data-using instruction is temporarily stored in a local register to be used by a second data-using instruction. Parallel processing techniques of squashing are used in the event that a prediction is erroneous.