WARF TECHNOLOGIES

Processing images made up of pixel data is an important task of many modern processors, especially in portable devices like cells phones and tablets. Sophisticated image processing often requires floating-point operations that must be repeated for millions of pixels. ‘Floating-point’ is a format for presenting numbers that is versatile and convenient but sacrifices some precision.

The energy consumed by floating-point processors in image-centric applications has a major impact on how long a device can operate between battery chargings.

UW–Madison researchers have developed a new circuit system for multiplying floating-point numbers. The system combines a traditional floating-point multiplier with a power-of-two multiplier that works by shifting operations. Substantial power savings may be realized by selectively steering some operands to the power-of-two multiplier.

The different circuits have different advantages. The floating-point multiplier uses more power but is more versatile, while the power-of-two multiplier uses less power but is less versatile.

• Integration into graphic processing units (GPUs)
• Particularly useful for smaller mobile devices

• Provides flexible tradeoff between versatility and power consumption
• Cuts execution energy by 35 percent
• Negligible impact on image quality
• May support ultra-high definition footage
• Easily implemented in hardware

Promising simulation have been run against industry-standard benchmarks.

Related Technologies

• WARF reference number P04398US describes a technique for decimal floating-point division.
• WARF reference number P04399US describes a technique for rapid decimal multioperand addition.

Tech Fields

• Information Technology : Computing methods, software & machine learning
• Information Technology : Image processing