Micro & Nanotech : Nanowires

Micro & Nanotech Portfolios


Carbon Nanotube Vacuum Field Emission Transistor Design for Large-Scale Manufacturing

Inventors from the Department of Engineering Physics at the University of Wisconsin-Platteville have created novel transistors by incorporating etched carbon nanotubes into a planar design that is compatible with existing fabrication techniques. In previous studies by others, aligned carbon nanotube transistors have been demonstrated to achieve saturation current that is 1.9 times higher than those that are silicon-based, at an equivalent charge density. In the optimal embodiment of this invention, carbon nanotubes are aligned and feature precise gaps that act as channels to allow the efficient transport of electrons without the need for a vacuum. The anticipated output of this approach will be nanoscale transistors that resist heat and radiation and operate at low voltage and high frequency. To address current challenges with large-scale VFET manufacturing, this technology offers three advantages – the carbon nanotubes can be prefabricated using methods that are already in place, the selective etching process for creating electron channels uses conventional integrated circuit techniques, and the planar design can integrate with existing wafer-based manufacturing methods.

Method for the Growth of Uniform 3-D Nanorod Networks

UW–Madison researchers have developed a method for growing 3-D nanorod networks in 3-D spaces, including highly confined spaces. The method is derived from atomic layer deposition (ALD), a state-of-the-art approach that has a growth rate independent of the precursor concentration owing to its self-limiting surface reaction. In this technique, however, higher temperatures and extended pulsing and purging times are implemented to allow networks of nanorods to grow uniformly along the inner surfaces of confined growth spaces.

The method begins by exposing a substrate in a growth chamber to precursor molecules at an elevated temperature, initiating a reaction. Next, the growth chamber is purged of the first precursor and exposed to a second precursor. This initiates a second reaction, after which the growth chamber is purged of the second precursor. These steps are repeated using exposure temperatures and durations such that the reactions result in layer-by-layer atomic construction of crystalline nanostructures within the growth chamber. The resultant interlinking structure may be extensive enough to form a nanostructure capable of maintaining its structural integrity even if the substrate is selectively removed. This is the first and only technique available to grow uniform 1-D nanostructures in 3-D confined spaces.

Durable Substrate for the Mass Production of Nanowires

Researchers at the University of Wisconsin – Stevens Point have developed a method for creating nanowires, including metallic, heterogeneous and nanowire assemblies, that is suitable for mass production. This method uses a durable diamond substrate, rather than the fragile HOPG substrate. A layer of conductive ultrananocrystalline diamond is formed on the surfaces of a planar silicon substrate. Integrated circuit techniques pattern the diamond to produce a well-defined edge upon which to grow the nanowire. An insulating layer of non-conductive ultrananocrystalline diamond may be placed on top of the patterned layer. Electromechanical deposition is used to grow the nanowire, which can then be easily removed and transferred to a secondary application substrate. The template is then reusable and nanowires have been created from a wide variety of metals.

Silicon Nanomembrane Thermoelectric Materials and Devices

UW-Madison researchers have developed methods for fabricating nanowires and nanoribbons that form the core of improved thermoelectric materials and thermoelectric devices. A lithography-based approach is used to construct nanowires and nanoribbons from semiconductor nanomembranes, such as silicon nanomembranes (SiNMs), which are single-crystal membranes from five to 200 nanometers thick. Epitaxial growth of nanostructures on free-standing wires leads to a periodic strain in the ribbon that is the equivalent of superlattice nanowires, but more easily produced in large quantities. Alternatively, the nanowires may be formed from alternating bands of different semiconductor materials.

Because the nanowires periodically vary in composition and/or strain along their length, minibands are formed that restrict the energies of charge carriers to a narrow range, optimizing the thermopower. In addition, the small size of the nanowires and these periodic variations lower the thermal conduction and increase the value of ZT, a dimensionless metric used to rate the efficiency of thermoelectrics.

Metal Silicide Nanowires and Methods for Their Production

UW-Madison researchers have developed a simple and unique method of forming single crystal metal silicide nanowires without a metal catalyst.  The free-standing nanowires are grown on a silicon substrate covered with a thin (1-2 nm) layer of silicon oxide via a simple chemical vapor deposition (CVD) process using single or multiple source precursors. Alternatively, the nanowires can be grown on the thin silicon oxide film via a chemical vapor transport (CVT) process using solid metal silicide precursors. The CVT process is particularly applicable for the growth of transition metal silicides for which organometallic precursors are not readily available.