Semiconductors & Integrated Circuits : Design & fabrication

Semiconductors & Integrated Circuits Portfolios


Semiconductor Quantum Dot Computer-Aided Engineering (CAE) Simulation Tool

A Professor of Electrical Engineering at the University of Wisconsin – Platteville has developed a software simulation tool for the computer aided engineering (CAE) of Quantum Dots. The CAE simulation tool accepts input of the QD parameters and then computes and returns the resulting optical and electronic properties. This includes QD structures with an InAs core and a GaAs matrix, and can be extended to any III-IV materials. The CAE tool simulates the most popular pyramidal and half-ellipsoidal QD shapes and can be extended to any arbitrary geometric shape. Compared with the often-incomplete results reported in the literature, this CAE simulation tool returns all possible electronic states within the QD. The CAE simulation results also supported the experimental data for the corresponding QD. The simulation tool currently runs as an application in the COMSOL platform and does not require a supercomputer for calculations and processing.

Carbon Nanotube Vacuum Field Emission Transistor Design for Large-Scale Manufacturing

Inventors from the Department of Engineering Physics at the University of Wisconsin-Platteville have created novel transistors by incorporating etched carbon nanotubes into a planar design that is compatible with existing fabrication techniques. In previous studies by others, aligned carbon nanotube transistors have been demonstrated to achieve saturation current that is 1.9 times higher than those that are silicon-based, at an equivalent charge density. In the optimal embodiment of this invention, carbon nanotubes are aligned and feature precise gaps that act as channels to allow the efficient transport of electrons without the need for a vacuum. The anticipated output of this approach will be nanoscale transistors that resist heat and radiation and operate at low voltage and high frequency. To address current challenges with large-scale VFET manufacturing, this technology offers three advantages – the carbon nanotubes can be prefabricated using methods that are already in place, the selective etching process for creating electron channels uses conventional integrated circuit techniques, and the planar design can integrate with existing wafer-based manufacturing methods.

Nitride Based Light-Emitting Diodes with Reduced Efficiency Droop

UW–Madison researchers have developed a new design for enhanced hole injection that uses heavily doped Si as the hole injector layer and Si/GaN tunneling heterojunctions to enable improvements in light emission efficiency. Two types of LED structures incorporating p-Si nanomembranes (NMs) and n-Si NMs as hole injectors were fabricated and characterized both electrically and optically in reference to the control device with conventional structures.

Compared to the reference LED devices, in terms of optical performances the light output power and normalized external-quantum efficiency (EQE) under the same electrical injection current (50 A/cm2) were improved for proposed LED structures with p-Si/GaN and n-Si/GaN tunneling hole injection junction by 29 percent and 100 percent, respectively.

Single-Crystal Halide Perovskite Nanowires with Superior Performance

Metal halide perovskite-based material is emerging as a “superstar” semiconductor material for cost-effective photovoltaic applications. UW–Madison researchers have developed a practical solution growth method for producing single-crystal perovskite nanowires with superior material quality and lasing performance.

Specifically the new method is based on a facile process of low-temperature dissolution of a metal precursor film in a cation precursor solution, followed by recrystallization to form single-crystal perovskite nanostructures such as nanowires, nanorods and nanoplates. Diverse families of metal halide perovskite materials with different cations, anions and dimensionality with different properties can be made to enable high-performance device applications.

Flexible MOSFET Phototransistors Maximize Light Sensing

UW–Madison researchers have developed an improved MOSFET design based on single-crystalline semiconductor film (or nanomembrane). The thin-film design maximizes light sensing because light is not blocked by any metal layer or component. The use of light reflectors further improves absorption. The new MOSFETs are fabricated on a polymer substrate that is mechanically flexible without degrading performance.

New Biodegradable Integrated Circuits Signal the Future of E-Waste Management

UW–Madison researchers have developed substantially biodegradable microwave integrated circuits and methods for their manufacture.

The circuits utilize cellulose nanofibril (CNF) thin-film paper rather than GaAs (a toxic semiconductor) as their principle substrate, minimizing amounts of potentially toxic inorganic materials. The CNF, which is derived from wood, is coated with a hydrophobic polymer to resist water and solvents while remaining readily degradable by common forest fungi.

Key electrical components, including a group III-V semiconductor, are formed on a standard substrate, which can be reused, and then transferred to the flexible, transparent and biodegradable CNF paper. The resulting circuits substantially reduce the levels of toxic materials introduced into the environment when they are discarded.

Flexible Thin-Film Transistors for Mass Production

UW–Madison researchers have developed a new approach for fabricating high performance radiofrequency TFTs. Their method enables mass production and takes advantage of recent improvements in nanoimprinting lithography (NIL) technology.

The new TFTs include a trench cut into the semiconductor layer that separates the source and drain regions. The trench provides the TFTs with a unique current flow path that helps prevent several issues (e.g., short channel effect) that typically arise at this scale. The fabrication process is so fine that the length of the channel region is on the order of submicrons.

Strain-Tunable Light Emitting Diodes Using Germanium

UW–Madison researchers have developed new tunable LEDs with germanium PIN heterojunctions. The diodes are made of an undoped (intrinsic) Ge layer between p-type and n-type doped Ge layers. The nano-thin structure can be epitaxially grown and then transferred to a flexible substrate.

Once bonded to the flexible substrate, the whole structure is stretched, causing biaxial tensile strain. Given sufficient strain, the Ge is transformed into a direct-bandgap semiconductor. When voltage is applied, radiation is emitted via electroluminescence. The wavelengths of the emitted radiation can be tuned by adjusting the amount of stretch (i.e., the amount of tensile strain) that is applied.

Block Copolymers for Sub-10 Nanometer Lithography

UW–Madison researchers have developed BCPs characterized by high Flory-Huggins interaction parameters (χ). They can self-assemble into domains having very small dimensions, and therefore are extremely useful in lithography.

The new BCPS may be polymerized from PHS monomers or from tert-butyl styrene and 2-vinylpyridine monomers. Overall degree of polymerization (N) can be experimentally controlled so that it’s high enough to form a desired phase (e.g., cylinders, spheres, lamellae, etc.) but low enough to produce very small dimensions.

New Surface-Modifying Film for BCP Formation

UW–Madison researchers have developed new surface-modifying layers made of crosslinked copolymer film. More specifically, the film is composed of styrene, (meth)acrylate and crosslinkable epoxy group-functionalized monomers.

Various styrene-containing BCPs can be deposited on top of the film and then subjected to conditions that cause them to self-assemble into vertically oriented domains.

Masks for Growing Nanopatterned Polymer Brushes

UW–Madison researchers have developed a method for growing nanopatterned polymer brushes using SI-ATRP. The method relies on making and using a lithographic mask.

The mask has three layers: a surface, a neutral layer and a block copolymer (BCP) film. The neutral layer serves two purposes. First, it induces the overlying BCP film to form vertical domains. Secondly, it provides initiating sites from which to grow the polymer brush chains.

Before that can happen, parts of the BCP film are selectively removed by etching. This forms a desired pattern of exposed regions. During SI-ATRP, these regions are exposed to a growth solution. The result is a polymer brush made of multiple chains, each of which is attached to the neutral layer.

Flexible Thin-Film Transistors Are Doped and Strained

UW–Madison researchers have developed doped semiconductor structures that share strain and enable thin, flexible transistors. The trilayer structures are made of single-crystalline semiconductor material like silicon and germanium.

The three-layered structure is grown epitaxially on a substrate and subsequently released. The first layer is selectively doped and comprises the same material and thickness as the third layer. This reduces the compressive or tensile strain typically borne by the middle layer.

Smoother Waveguides for More Efficient Nonlinear Frequency Conversion

UW–Madison researchers have developed a method for fabricating OPGaAs two-dimensional semiconductor-based waveguides having extremely low layer-interface roughness.

The structure is grown on a template using standard techniques and comprises a core sandwiched between upper and lower cladding layers. The layers have different, periodically arranged crystalline orientations. The surfaces between each layer undergo chemical polishing and isotropic etching that can be done in situ. A high-refractive-index ridge projects above the upper cladding layer and runs along the direction that light propagates. Known lithographic techniques and a combination of wet and dry etching create straight, smooth sidewalls.

Semiconductor Interconnect Design for Small, Inexpensive, Integrated Current Sensing with Improved Reliability

UW–Madison researchers have developed a design for integrated current sensing that is comprised of semiconductor interconnects with a loop configuration, instead of a straight bar, and point magnetic field detectors specially located to detect current flowing in the interconnect from DC to high frequency (MHz). Giant magnetoresistive (GMR) detectors serve as these point-field detectors.

Making Large-Scale Nanopatterned Arrays by Streamlined Roll-to-Roll Printing

UW–Madison researchers have developed a roll-to-roll apparatus for transferring large areas of nanoscale elements from their rigid manufacturing surface to a flexible material without spacing errors or damage.

First, a substrate containing the nanopatterned components, such as a stiff wafer, is overlaid with a flexible sheet coated with an adhesive. Rollers convey the sheet across a contacting wheel that presses the sheet and wafer together, lifting and attaching the elements at the area of contact. The method can be performed as a single step or in parallel to move multiple elements at a given time.

Low-Temperature Method for Smoothing the Disordered Edges of Graphene

UW–Madison researchers have discovered a technique that reduces the required temperatures for edge restructuring of graphene. With this technique, the disordered edges of the material can be smoothed and straightened at temperatures below 1000°C. Because this technique effectively repairs the disordered edges, the current method of top-down etching can still be used to create graphene.

New Method for Direct Patterning in Block Copolymer Lithography

UW–Madison researchers have designed a polymer brush that may be used in underlying buffer or imaging layers for block copolymer lithography. These low molecular weight block copolymers (brushes) can be anchored to substrate surfaces to provide a non-preferential buffer layer for the assembly of higher molecular weight block copolymer thin films. The higher lithographic sensitivity of the brushes allows for shorter processing time and a reduction in the number of steps involved with the assembly process. It also allows for more predictable control over the contrast in chemical pattern and provides a lower defect density in the assembled BCP.

This discovery combines bottom-up and top-down approaches into a single system involving depositing a block copolymer solution on a patterned buffer or imaging layer on a substrate and then inducing the BCPs to separate into domains. The direct patterning and assembly approach presents notable simplification with regards to BCP processing. 

Low-Noise, Phase-Insensitive Linear Amplification at Microwave Frequencies

UW–Madison researchers have developed a system and method for a low-noise, phase-insensitive linear amplifier capable of accommodating readout signals from quantum computing applications, even when such signals reach frequencies in the RF and microwave range. The amplifier can improve signal-to-noise ratio significantly by incorporating a low-inductance device geometry that is compact, straightforward to model at microwave frequencies and readily integrated into an RF or microwave transmission line environment. The device’s input and output can be matched to transmission-line impedances.

The amplifier system includes an input providing a direct coupling configured to receive a high-frequency input signal. The system also includes an amplifier containing a dielectric material separating superconducting layers, forming an amplifier loop configured to receive the input signal and deliver an amplified signal. The system includes an output providing a direct coupling configured to deliver the amplified signal. A quantum information processing network is configured to receive and relay high-frequency signals. The network includes a signal source, a source of qubits and a linear cavity resonator. The network also includes a transmission line communication system configured to transmit and receive the high-frequency signal, and an amplifier coupled directly to the transmission line communication system through an input and output.

Method to Manage Active Leakage Power in Power Gated Integrated Circuits

UW–Madison researchers have developed an improved leakage power management technique using programmable power gating transistors. The method addresses the problems of oversized PG devices and active power leakage by changing the number of active power gating transistors as a function of usage-time and temperature to decrease leakage current when the PG transistors are in the on or wake state.

An integrated circuit includes multiple PG transistors connected in parallel that selectively control power to the integrated circuitry according to a sleep/wake signal used for power conservation. A transistor aging detector generates a signal reflecting aging of the power gating transistors. This signal controls the PG transistors to compensate for a decrease in PG transistor current flow as the PG transistors age. The PG transistors have different control inputs connected to the sleep/wake signal and the transistor-aging detector increases a number of control inputs connected to the sleep/wake signal as the PG transistors age. The technique decreases unnecessary leakage current early in the life of an integrated circuit by avoiding the need to oversize the PG transistors to accommodate end-of-life-cycle degradation of the transistors. As a result, supply voltage may be better tailored to minimize current leakage when the integrated circuit is young or operating at low temperatures.

Large-Area, Nanoperforated Graphene Materials for Semiconducting Applications

UW–Madison researchers have developed methods to fabricate nanoperforated graphene by etching periodic arrays of nanoscale holes into graphene sheets. The features of the periodic array of holes, including diameter, spacing and constrictions between holes, can be fabricated with dimensions smaller than 20 nm and are designed to provide an electronic band gap of at least 100 meV.

The methods comprise forming an etch mask that defines a periodic array of holes over single or multiple layers of graphene material that has been grown or deposited onto a support material. A perforated structure is formed by depositing and patterning the masking layer onto the graphene via a pattern-defining block copolymer, which may also include a wetting and a neutral layer. Once patterned, the graphene is etched to form interconnected graphene strips that behave as semiconductors with a sufficient band gap. The method provides control over the size and pattern of the holes, which allows the material to be tailored for specific material properties and applications.

Wrapper Cell for Hierarchical System-on-Chip Testing

UW–Madison researchers have developed an improved wrapper cell design for hierarchical integrated circuits with significantly reduced complexity as compared to currently available designs. The improved design may reduce area of the integrated circuit by approximately 13 to 23 percent through reduced gate count and simplified wiring. In addition, the improved design makes it possible to use the same wrapper cell for both input and output data monitoring, which helps reduce the cost of the cell library. The design is simplified through eliminating a multiplexer and providing fewer interconnections between elements.

High-Frequency Bridge Suspended Diode for Power Generation from High Frequency Microwave Sources

UW-Madison researchers have developed full metal electrical nano-diodes and a method to fabricate such diodes with desirable properties for high-frequency applications. The diodes produced by this method have an ultra-high cutoff frequency, since most of the surrounding dielectric material is removed. The method involves a metal-coated semiconductor structure, which is further coated with a Teflon-like layer. The semiconductor substrate material is then etched, leaving islands of metal suspended by the Teflon-like material. The suspended islands operate as coupled MIM junctions. This structure functions as a freely suspended diode with reduced parasitic junction capacitance.

Improved Method to Create and Transfer Nanoscale Patterns Using Self-Assembling Block Copolymers

UW-Madison researchers now have developed an improved method of creating and transferring chemical or physical nanoscale patterns using block copolymers.  This method builds upon the researchers’ previous inventions by controlling the chemistry of the copolymer pattern to facilitate reactions that lead to transferring of the chemical or physical patterns.   The copolymers used in such an approach comprise two or more constituent units engineered to exhibit distinct chemical properties based on blocking of monomer units and branching thereof.  Different chemical properties among monomer units establish micro-phase separation at the polymer surface and allow ink or transfer molecules to be sequestered into specific copolymer blocks to generate distinct patterns.  The ink molecules are designed to interact with a second substrate, commonly by raising the temperature just above the glass transition temperature, to facilitate mass transfer of the ink and reproduce the copolymer template pattern.

Traditional lithography techniques can be incorporated into the new method, creating the master template to which the copolymers are adhered.  The master template also can be fabricated via chemically nanopatterned surface techniques.  The master template is regenerated after each use, but also may be replicated given specific inks that facilitate the bonding of a new copolymer surface after initial copying.  This method can be used to rapidly and easily generate chemical or physical patterns to be employed in all fields of nanotechnology, such as manufacture of integrated circuits.

Vertical Cavity Light Sources Based on Stacked Membranes

UW–Madison researchers in collaboration with researchers at the University of Texas at Arlington have developed a system and method to fabricate vertical cavity light-emitting sources that utilize patterned membranes as reflectors. The vertical cavity light-emitting sources have a stacked structure that includes an active region placed between an upper reflector and a lower reflector. The active region and upper and lower reflectors can be fabricated from single or multilayered thin films of solid state materials or membranes, which can be processed separately and stacked to form a vertical cavity light-emitting source. As a result, the vertical cavity light-emitting sources can be compact, with thickness smaller than 3 µm.

The use of patterned membranes as reflectors makes it possible to eliminate thick mirror reflectors from the vertical cavity light-emitting source structure, which facilitates high-density array fabrication on a single substrate. In addition, by tailoring the structural parameters of the patterned membranes, different vertical cavity light-emitting sources in an array can be tailored to produce different output radiation wavelengths from ultraviolet through far-infrared.

Multilayer Si/SiO2 Semiconductors for Photoelectric Device Fabrication

UW-Madison researchers have developed an improved method for manufacturing quantum-well photoelectric devices from monocrystalline semiconductor layers.  The proposed invention aims to address the limitation of current technology with the use of Si charge carrying layers in between silicon dioxide (SiO2) barrier layers, allowing operation at room temperature and with wavelengths in the visible region.  The method used to fabricate these layers is similar to the previously developed technology except a different barrier material is used to promote electron confinement.

This method uses standard integrated-circuit deposition techniques and strain-symmetrization to produce superior virtual substrates upon which multiple layers are grown.  The process starts with the SOI substrate, a well characterized and developed technology commonly used in the integrated-circuit industry to fabricate Si computer chips.  The SOI base is thinned and smoothed using chemical or mechanical processes.  The alternating silicon/silicon dioxide layers then are grown on the SOI using standard deposition techniques.  The strain produced by the lattice constants of the two different materials is relieved by physically removing the layers from the SOI, creating a virtual substrate. 

The multiple growth and removal of the multilayer structure reduces the amount of defects in the crystal lattice, resulting in increased device power.  More layers can be grown on the virtual substrate to produce a component layer, but the number of grown layers is limited to reduce imperfections in the crystal lattice.  The multilayer structures then can be annealed to produce stacks of Si semiconductor of the desired thickness.  These semiconductors can be used to produce inexpensive and easily integrated quantum-well photoelectric devices, which have potential applications in chemical sensors, LEDs and all digital devices.

Ferroelectric Thin Films for Improving Memory Technology

UW-Madison researchers have developed a method for fabricating and transferring BiFeO3 thin films onto a variety of substrates, thereby allowing limitless strain control. The BiFeO3 layer can be epitaxially grown over a variety of materials, called perovskite, with the same type of crystal structure as calcium titanium oxide.

The perovskite layer functions as a buffer to protect the thin film during the chemical release process. Additionally, it improves the epitaxial growth of strain-free BiFeO3 layers on different sacrificial substrates. Once released from their original sacrificial substrates, the free-standing BiFeO3-perovskite heterostructures may be transferred onto a variety of host substrates to exhibit improved ferroelectric characteristics that include increased remnant polarization, reduced coercive field, reduced leakage current, and/or reduced fatigue.

This new fabrication method expands the prospect of fine tuning BiFeO3 thin film characteristics to advance memory technology.

Thin-Film Semiconductor for Increasing Microprocessor Speeds

UW-Madison researchers have developed a method for fabricating a heterogeneous semiconductor structure that enhances both electron and hole mobility. This method extends a previous patent (see WARF reference number P06047US) to allow the fabrication of mixed-crystal-orientation silicon that incorporates the hole mobility enhancing strained Si(110) with the high electron mobility of Si(001).

During fabrication, a thin, single-crystal silicon membrane with regularly patterned holes is applied on a silicon substrate with a different composition, orientation or strain state. The holes then are filled by growing up the bottom layer. Alternatively, the bottom silicon semiconductor layer is patterned with regularly spaced holes. Then a second single-crystal membrane with a different composition, orientation or strain state is applied as a layer over the first and fills the holes. When the top is smoothed, islands of the second layer remain, surrounded by the first. The difference in crystalline orientation, semiconductor composition and/or degree of strain between the silicon layers results in one type of silicon experiencing enhanced electron mobility while the other experiences enhanced hole mobility.

Method for Improving Plasma Processes by Controlling a Voltage Waveform

A UW-Madison researcher has now developed an improved algorithm that significantly enhances plasma etching through an automated process that modulates a voltage waveform applied to the substrate material until the optimal bombarding ion energy distribution is achieved.

To control the ion energy distribution, the inventor used a programmable waveform generator in combination with a power amplifier to tailor the waveform shape of the radio frequency (RF) bias voltage applied to the substrate during processing. The technique works by introducing a periodic bias voltage to the semiconductor substrate through a direct current (DC) blocking capacitor, which has a waveform comprised of voltage pulse peaks.

A fast Fourier Transform (FFT) of the substrate waveform is compared, one frequency at a time, with the FFT of a desired “target” waveform, to determine adjustments needed at the waveform generator. An inverse FFT then yields the waveform generator output. It is repeated until the substrate waveform converges to the targeted shape, providing a quick systematic method for producing an arbitrary distribution of ion energies at the substrate.

This iterative procedure is vital to making the system, previously done manually, fully automated. It has been verified for several target waveform shapes.

Using Block Copolymer Materials to Form Patterns with Isolated or Discrete Features

The UW–Madison researchers have expanded their previous work to include methods for directing the self-assembly of block copolymers to form patterns with isolated structures such as those used in the fabrication of integrated circuits. They start with a chemically patterned or otherwise activated surface. These surfaces direct the morphology of the overlying block copolymer films to be oriented parallel to the surface in unpatterned regions or in regions with relatively large patterned features and oriented perpendicular to the surface in regions with the smallest patterned features. This allows block copolymers to form complex circuit designs from patterns with isolated features as small as a few nanometers.

Progressive Random Access Scan Circuitry

UW-Madison researchers have developed a method and circuitry for a new integrated circuit test, called Progressive Random Access Scan (PRAS), which functions like RAS but requires less expensive hardware. PRAS combines the matrix-based data access method of RAS with the architecture of serial-scan. A static random access memory cell is hybridized with a storage element, combining functions used in RAS so that PRAS requires less space, time and energy.

Method for Fabricating High-Speed Thin-Film Transistors

UW-Madison researchers have developed a method of fabricating high-speed thin-film transistors on flexible membranes that produce a maximum frequency of 7.8 gigahertz or more. Rather than processing the single-crystal silicon layer on a flexible substrate, it is processed on a heat-resistant bulk silicon substrate and moved to a flexible one. A hydrogen implantation layer lies between the silicon and the substrate. The silicon is split from the bulk silicon substrate at the hydrogen layer, and attached to a flexible polymer substrate using adhesive.

Metal Silicide Nanowires and Methods for Their Production

UW-Madison researchers have developed a simple and unique method of forming single crystal metal silicide nanowires without a metal catalyst.  The free-standing nanowires are grown on a silicon substrate covered with a thin (1-2 nm) layer of silicon oxide via a simple chemical vapor deposition (CVD) process using single or multiple source precursors. Alternatively, the nanowires can be grown on the thin silicon oxide film via a chemical vapor transport (CVT) process using solid metal silicide precursors. The CVT process is particularly applicable for the growth of transition metal silicides for which organometallic precursors are not readily available.

PIN Diodes for Fast Photodetection, and High-Speed, High-Resolution Imaging and Sensing

By employing improved methods for integrating Si and Ge in thin multilayer structures, or “nanomembranes” (see WARF reference number P04286US), UW-Madison researchers have created PIN diodes in which the intrinsic layer is Ge or SiGe and the p-type and n-type layers are silicon. In some applications, these nanomembrane PIN diodes are fabricated on a solid silicon-on-insulator support. In others, the nanomembranes are released from the support and transferred to flexible substrates, such as plastic films.

Method for Double-Sided Processing of Thin-Film Single-Crystalline Electronics

UW-Madison researchers have developed methods for fabricating active semiconductor devices, including thin-film transistors (TFTs) and more complex devices, on single-crystal semiconductor membranes and transferring these membranes to many types of substrates, including glass, plastics, Si, and other membranes. They also have developed methods for the two-sided processing of these single-crystal semiconductor membranes.

The methods start with a substrate that includes an active layer composed of a single-crystal semiconductor supported on a sacrificial layer. Device components are fabricated on the upper surface of this active layer. The active layer is released from the sacrificial layer, creating a thin single-crystal membrane that is transferred to a new host substrate. During the transfer process, the membrane containing devices on its upper surface is “flipped,” so the devices are on the bottom next to the host substrate. Additional device components can then be fabricated on the original lower membrane surface. The host substrate may become part of the electronic device, or it may temporarily support the active layer before it is transferred to an integration platform. The process can also be repeated, so that a stack of double-side processed membranes is created, leading to a new method of 3-D integration.

Efficient Statistical Timing Analysis of Circuits

UW-Madison researchers have developed a systematic STA solution that takes into account correlations caused by global variations and path reconvergence. They extended the commonly used canonical timing model to represent all timing variables in the circuit as a weighted linear combination of a set of independent random variables. A variation vector consisting of all these weights is used to specifically represent both global and path correlation information.

Determining Film Stress from Substrate Shape Using Finite Element Procedures

UW-Madison researchers have developed a method for analyzing the magnitude and spatial distribution of stress in thin films applied to substrates such as those used in the fabrication of integrated circuits and similar microelectronic and micromechanical devices. The method uses experimentally measured substrate shape data and finite element analysis to determine all characteristics of a thin-film stress field. First, the substrate is analyzed by itself to obtain the finite element nodal forces at the top surface of the substrate. Then the film is analyzed separately using these nodal forces as known loads to determine the stresses they will produce in the thin film.

Fabrication of Magnetic Tunnel Junctions with Epitaxial Ferromagnetic Layers

UW-Madison researchers have developed a new fabrication method that allows both the top and bottom FM layers to grow into strong texture or epitaxial structures on a variety of substrates, including silicon. In this method, a two to three nanometer top FM layer is deposited before, rather than after, the oxidation of the tunnel barrier metal. All three layers are strong texture or epitaxial structures. Next, the stack is exposed to a gas mixture to selectively oxidize the tunnel barrier metal. Finally, more FM and capping layers are epitaxially grown on the stack to produce a high quality MTJ.

Improved Fabrication of Strained Silicon Multilayer Structures

UW-Madison researchers have developed a new approach for creating a strained layer of silicon that takes advantage of the commercial availability of silicon-on-insulator (SOI) substrates. A layer of silicon-germanium (SiGe) is grown on an SOI substrate. Because germanium has a larger lattice constant than Si, the SiGe layer is compressively strained as it grows. A layer of unstrained Si is formed on top of the SiGe layer, potentially followed by another compressively strained SiGe layer and another Si layer. Next, the structure is lithographically patterned to open access holes to the buried SOI layer, and the SOI layer is preferentially etched to release the multilayer structure. Release of the multilayer structure partially relaxes the SiGe layer(s) and elastically strains the Si layer(s). The fully released multilayer structure can then be mounted on the flat or curved surface of a selected substrate to form specific devices.

Fabrication of Oxide Barriers Using Selective Oxidation of Metallic Thin Films

UW-Madison researchers have now demonstrated that by performing the oxidation step under an atmosphere composed only of CO and CO2 gases, they can completely and selectively oxidize only the tunnel barrier layer in magnetic tunnel junctions. A CO/CO2 gas mixture provides a much lower partial pressure of oxygen than can be achieved when pure oxygen is used as the oxidizing gas.

By tuning the CO/CO2 gas ratio, the researchers easily oxidized a tunnel barrier layer made of aluminum without oxidizing neighboring ferromagnetic layers composed of a cobalt/iron alloy. In essence, the method works because some materials, such as aluminum, will oxidize easily under very low partial pressures of oxygen, while others, such as cobalt, will not.

Spin Readout and Initialization in Semiconductor Quantum Dots

UW-Madison researchers have now developed a semiconductor-based, quantum dot scheme for enabling measurement of the spin states of individual qubits without the need for additional external couplings that can cause decoherence. In this quantum dot scheme, the energy levels of trapped qubits are controlled by varying the voltages of nearby metal gates. By bringing specific energy levels into resonance with an applied microwave field, the qubits can be made to undergo spin-dependent oscillations that are detected by a single electron transistor.

Method for Countering Lattice Mismatch Between Different Semiconductor Materials

UW-Madison researchers have developed a technique for controlled integration of different semiconductor materials, resulting in thin films of desired morphologies. The technique involves producing and maintaining a tensile or compressive stress in a silicon substrate, which counters the natural lattice mismatch between the silicon and the semiconductor material (e.g., germanium) grown on top. The stress in the silicon substrate is produced by microstructures of silicon nitride, which are deposited beforehand by exposing the substrate to ammonia and silane gases in a CVD process. By adjusting the gas ratio, the stress, and thus the lattice parameters, can be precisely controlled, allowing growth of thin films with desired properties. 

Method for Bonding Stacks of Silicon Layers by Electromagnetic Induction Heating

UW-Madison researchers have now found that EMIH can in fact be used to generate an ohmic silicon response, which directly heats the silicon. After stacking silicon wafers on top of each other, an EM field is generated that intersects the stack of wafers and heats them to a predetermined temperature.

Solid-State Quantum Dot Devices for Quantum Computing

An interdisciplinary team of UW-Madison physicists, engineers and materials scientists has now designed a scalable, multilayer semiconductor device that can be used to build a quantum computer. Fabricated by growing layers of semiconductors and patterning electrostatic gates on the surface, this quantum dot device traps individual electrons in a solid, brings the electrons close to each other, maintains the electrons’ phase coherence and allows manipulation of the electrons’ individual spin states.

Method for Measuring Thin Film Stress from Substrate Displacement

A UW-Madison resesarcher has developed a novel method for calculating thin film stress based on an inverse finite element analysis of the displaced substrate wafer. This technique produces accurate measurements regardless of whether stress is constant across a wafer, and can be employed with any system that measures substrate curvature.

Method and Apparatus for Etching and Deposition Using Microplasmas

UW-Madison researchers have developed a method for generating and using spatially localized microplasmas operating in parallel with one another to add or remove material over large substrate areas. This means that a plasma can be developed in a specific region, which is tailored to the treatment requirements of that region.