WARF: P02006US

Method for Countering Lattice Mismatch Between Different Semiconductor Materials


Amit Lal, Max Lagally, Chung Hoon Lee, Paul Rugheimer

The Wisconsin Alumni Research Foundation (WARF) is seeking commercial partners interested in developing a technique for controlled integration of different semiconductor materials to produce thin films with desired properties.
OVERVIEWThe ability to grow thin films of materials with special properties onto a base semiconductor, such as silicon, is critical to enhancing the utility of integrated circuits. For example, the ability to grow germanium on silicon could lead to transistors with integrated optics capability and the capacity to operate at much higher frequencies.

A major obstacle to growing thin films of one semiconductor on another is the lattice mismatch between materials. Lattice mismatch causes the film to adopt a strain-induced morphology, which in turn adversely affects the film’s electrical and optical properties.
THE INVENTIONUW-Madison researchers have developed a technique for controlled integration of different semiconductor materials, resulting in thin films of desired morphologies. The technique involves producing and maintaining a tensile or compressive stress in a silicon substrate, which counters the natural lattice mismatch between the silicon and the semiconductor material (e.g., germanium) grown on top. The stress in the silicon substrate is produced by microstructures of silicon nitride, which are deposited beforehand by exposing the substrate to ammonia and silane gases in a CVD process. By adjusting the gas ratio, the stress, and thus the lattice parameters, can be precisely controlled, allowing growth of thin films with desired properties. 
  • Production of specific arrays of quantum dots with controlled size distributions
  •  Flat, two-dimensional films of high germanium content
  • Allows controlled integration of different semiconductors to create unique material combinations, such as silicon-germanium
  • Microstructures for controlling strain can be produced by lithography and scaled to sub-micron dimensions.
  • Applicable at both the wafer scale and die levels
  • Suitable for parallel, batch fabrication of multiple semiconductor devices
For More Information About the Inventors
Contact Information
For current licensing status, please contact Mark Staudt at or (608) 265-3084.
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