WARF: P130143US02

Dynamic Bandwidth Scaling Improves Energy Efficiency


Nam Sung Kim, Daniel Chang, Hoyoung Kim

The Wisconsin Alumni Research Foundation (WARF) is seeking commercial partners interested in developing a method to determine based on workload the optimal number of I/O pins needed for digital signal processors.
OVERVIEW3-D main memory is an emerging technology in which stacks of DRAM are situated underneath the processor. This configuration helps decrease main memory latency while allowing designers to increase main memory bandwidth. The technology was initially designed to allow streaming multimedia applications to run on digital signal processors (DSPs) found in mobile devices.

The technology also supports a larger number of input/output (I/O) pins found in processors. However, wider I/O (i.e., more pins) can waste energy and does not always translate to better performance. Finding a way to determine the best number of pins for a given workload would be advantageous.
THE INVENTIONUW–Madison researchers and others have developed a ‘scheduler’ to dynamically scale the number of I/O pins depending on workload characteristics. The scheduler increases main memory bandwidth during memory intensive phases of a program to reduce the number of main memory accesses, then decreases the bandwidth when it is no longer needed.

Key metrics are used to identify the optimal number of I/O pins, such as instructions per cycle, utilization of execution units and the number of consecutive cache misreads.
  • Optimizing DSPs with 3-D stacked DRAM
  • Considerably improves performance and energy efficiency
Contact Information
For current licensing status, please contact Jeanine Burmania at or 608-960-9846.
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