Wisconsin Alumni Research Foundation

Technology

Improving Memory Access in Asymmetric Memories

In computer memory there is a tradeoff between capacity (how much data can be stored) and latency (how quickly it can be accessed). To achieve a balance, typical memory systems employ a hierarchy of d...
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Nam Sung Kim, Hao Wang | P150172US01

Technology

Managing Memory in Virtualized Computer Systems

Computer programs access memory using virtual addresses, which are translated by hardware into unique physical addresses that locate the data in the cache or memory. The set of virtual addresses acces...
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Mark Hill, Michael Swift, Jayneel Gandhi | P150108US01

Technology

Qubit Measurement System Is Efficient, Scalable

In the field of quantum computing, the performance of quantum bits (‘qubits’) has advanced rapidly in recent years. A truly scalable system requires the ability to rapidly and accurately m...
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Robert McDermott, Frank Wilhelm-Mauch, Britton Plourde, Maxim Vavilov, Luke Govia, Emily Pritchett | P140246US01

Technology

Improved Gate Design for Quantum Computers

Some extremely complex tasks – like sorting very large databases or factoring large numbers – are challenging for classical computers. Quantum computers can solve such problems because they use qu...
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Mark Eriksson, John Gamble, Daniel Ward, Susan Coppersmith, Mark Friesen | P130184US02

Technology

Computer Accelerator System Boosts Efficiency

Hardware accelerators improve computer performance by allowing the main processor to off-load certain tasks, for example, processing floating-point or graphics calculations. The accelerator is designe...
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Karthikeyan Sankaralingam, Chen-Han Ho, Sung Kim | P140164US01

Technology

Managing Computer Power and Performance

Energy consumption is a major constraint in computer design because of factors like power costs, operating life and heat. The tradeoff between energy consumption and performance is managed to some deg...
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David Wood, Rathijit Sen | P140071US01

Technology

More Accurate Branch Predictor Circuit

A branch predictor is a digital circuit that attempts to direct traffic in an instruction stream. Branching is usually implemented with a conditional jump instruction, and branches may be ‘taken’ ...
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Mikko Lipasti, Dibakar Gope | P140330US01

Technology

Predicting Logic Gate Failure

Logic gates are the building blocks of integrated circuits. They use multiple transistors to receive and interpret voltage inputs, then provide outputs. Future generations of integrated circuit micr...
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Karthikeyan Sankaralingam, Raghuraman Balasubramanian | P130365US01

Technology

Maximizing Multicore Processor Performance

Computer processors typically include a number of central processing unit (CPU) cores for executing instructions. Each core is capable of reading and executing a sequence of instruction code, or ‘th...
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Nam Sung Kim | P130137US01

Technology

Ultra-Efficient Continuous Monitoring of Sensors

Tracking emissions, sensing earthquakes and monitoring patient brain waves are just a few of the applications that rely on changing, real-world information. In typical systems, sensors pass on raw dat...
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Mikko Lipasti, Atif Hashmi, Andrew Nere, Giulio Tononi | P130049US01

Technology

SuperTag Cache for Energy-Optimized Compression

Cache memories play a critical role in reducing a computer system’s energy. Generally, they are fast access memories that store data reflecting locations in a corresponding main memory. Typically, t...
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David Wood, Somayeh Sardashti | P130076US01

Technology

LEAP - Improved Data Lookup for High-Speed Routers

Networks allow data exchange between linked computers. Data messages are divided into packets, which are able to navigate complex and changing networks. A router, or switch, reads packet addresses and...
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Karthikeyan Sankaralingam, Eric Harris, Samuel Wasmundt | P120239US01

Technology

SISO Model Predictive Controller

Currently, most single-input, single-output (SISO) systems use a proportional, integral, derivative (PID) controller. The PID controller is simple, fast, and easily implemented on simple computing har...
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James Rawlings, Gabriele Pannocchia, Nabil Laachi | P04113US

Technology

Adaptive Cache Compression System

The speed at which a computer executes its workload is constrained by the time it takes for data and instructions to be transferred from its memory to its processor. To reduce this “memory laten...
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David Wood, Alaa Alameldeen | P04273US

Technology

Scalable Monitor of Malicious Network Traffic

UW-Madison researchers previously described a system of analyzing malicious network traffic to automatically generate signatures that may be used by a network intrusion detection system (NIDS) to prot...
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Paul Barford, Vinod Yegneswaran, David Plonka | P05182US

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