WARF TECHNOLOGIES

Modern computer processors can process data faster than the data can be exchanged with external memory. For this reason there is considerable interest in boosting the ‘bandwidth’ of the memory bus that communicates between processors and external memory. Improved bandwidth would allow faster data transfers and better utilize processor speed.

The bandwidth of a memory bus is determined by two factors: its width and transmission speed. However, simply increasing width is not physically practical while increasing speed can degrade data.

UW–Madison researchers have developed a system to substantially increase memory bus bandwidth by combining a parallel memory bus with a high-speed serial memory bus. A serial memory bus normally introduces too much latency (data delay) for general computer processors, but this can be accommodated using special processors like GPUs or streaming processors.

By selectively steering some memory traffic to the serial memory bus, total memory bandwidth is significantly increased while still providing low latency when needed via the parallel memory bus.

• Heterogeneous processors with off-chip memory (for mobile, desktop and data mining usage)

• Boosts memory bandwidth
• Respects physical constraints
• Enables extremely high rates of data transmission without skew
• Can be flexibly implemented in hardware, software or both
• Reduces crosstalk
• Simple architecture
• Operates dynamically
• Requires no specific program modifications

Simulations show favorable results based on industry standard benchmarks.

Related Technologies

• WARF reference number P120224US01 describes a method for high-speed data transfer between GPUs and their off-chip memories.

Tech Fields

• Information Technology : Computing methods, software & machine learning
• Information Technology : Hardware