WARF TECHNOLOGIES

For integrated circuits such as very large scale integrated (VLSI) circuits to work properly, signals traveling on them must arrive at their destination at the proper time. However, there are many sources of timing variations, including flaws in manufacturing, densely integrated elements and power dissipation.

Statistical methods for calculating the timing variations and signal arrival time use either a flawed assumption of linear signal delays or exponentially increase in complexity with circuit size, resulting in a slow and impractical analysis.

UW-Madison researchers have developed an accurate statistical timing analysis for integrated circuits that efficiently predicts signal delay. They created a quadratic timing model that partitions the circuit into approximately equal elements and assumes uniform properties for each element. The analysis provides information about the signal delay and determines whether it is small enough for the system to operate correctly.

• Analyzing timing variations in integrated circuits

• Exhibits a linear—instead of exponential—increase in complexity with circuit size and variation sources
• Offers adjustable resolution: the user can choose the size of the divided elements, with accuracy balanced against computation time
• Provides faster analysis than Monte Carlo simulation
• Provides more accurate analysis than block-based or path-based statistical timing analysis
• Low computational cost

For More Information About the Inventors

• Yu Hen Hu

Tech Fields

• Information Technology : Computing methods, software & machine learning