Wisconsin Alumni Research Foundation

Information Technology
Information Technology
Memory Processing Core Architecture
WARF: P140414US02

Inventors: Karthikeyan Sankaralingam, Jaikrishnan Menon, Lorenzo De Carli


The Invention
Aspects of the present invention provide a memory system comprising a plurality of stacked memory layers, each memory layer divided into memory sections, wherein each memory section connects to a neighboring memory section in an adjacent memory layer, and a logic layer stacked among the plurality of memory layers, the logic layer divided into logic sections, each logic section including a memory processing core, wherein each logic section connects to a neighboring memory section in an adjacent memory layer to form a memory vault of connected logic and memory sections, and wherein each logic section is configured to communicate directly or indirectly with a host processor. Accordingly, each memory processing core may be configured to respond to a procedure call from the host processor by processing data stored in its respective memory vault and providing a result to the host processor. As a result, increased performance may be provided.
Additional Information
For More Information About the Inventors
For current licensing status, please contact Jeanine Burmania at [javascript protected email address] or 608-960-9846

WARF