UW-Madison researchers led by Profs. Michael Arnold and Padma Gopalan have developed the first commercially viable method for aligning carbon nanotubes to create high-performance semiconductors that can significantly outperform silicon and meet the aggressive needs of next-generation electronic devices.
The majority of the $425 billion semiconductor market still relies on silicon, a technology that’s been used for more than 50 years and unable to meet the aggressive demands for continuing innovation in electronic devices. A rival material, called carbon nanotubes, are atomically thin rolls of carbon that act like small semiconducting wires. Carbon nanotubes conduct more current per area than silicon and their high surface area makes them extremely sensitive and responsive.
Though carbon nanotube semiconductors have the potential to outperform silicon, a successful commercial process for effectively using them has not emerged. In raw form, carbon nanotubes exist in a disordered state and conduct electricity poorly. For carbon nanotubes to be most useful in electronic applications, the nanotubes must align in the same direction in a single layer so that electricity can rapidly and efficiently travel across the wires. This has been one of the long-standing obstacles to adoption of carbon nanotubes in the electronics industry.
The Arnold/Gopalan team report the first commercially viable process for controlling the orientation of carbon nanotubes. Their three-step process involves 1) use of a wrapping polymer sorting process to quickly purify carbon nanotubes from commercially available powder, 2) creation of a concentrated ink of the carbon nanotubes, and 3) deposition of a film of aligned carbon nanotubes on a surface by either injecting the ink across the surface or pulling the surface through a liquid interface containing the aligned carbon nanotubes.
This process leverages chemistry, self-assembly and flow phenomena for rapid, low-cost, unparalleled control of carbon nanotube deposition and alignment on numerous different surfaces. It requires mild processing conditions and minimal optimization of equipment already common to the fabrication industry. It produces wafers that can be directly integrated into chips and device fabrication workflows, without special accommodations that are typically required for advanced manufacturing technologies.
This technology operates in the global semiconductor and circuit manufacturing market and can enable development of next-generation logic chips, radio frequency components and conductive films – amounting to $130 billion in market value. The alignment process is enabling for development of new electronics and can also grow the semiconductor markets significantly. For example, the ability to create single layers of semiconducting films facilitates transparent conductive films for use in transparent displays and flexible printed circuit boards, expected to be worth $53 billion globally by 2026.
The method has been shown to create uniform thin films of aligned carbon nanotubes on silicon and quartz wafers of up to 4 inches in diameter and demonstrated an order of magnitude more efficient electrical conductivity, which can enable devices that are 10x faster or have 10x longer battery life with the same power consumption. Additionally, the method has been used to selectively deposit aligned carbon nanotubes on silicon wafers to create functional high-speed transistors that outperform silicon. These aligned carbon nanotube transistors have 10x higher current density, enabling faster switching without significant increases in power consumption.
Arnold, Michael S. “Globally Aligned, Wafer-Scale Deposition of Carbon Nanotubes Via Interfacial Assembly.” ECS Meeting Abstracts. No. 11. IOP Publishing, 2021. https://doi.org/10.1149/MA2021-0111548MTGABS
Read more: Carbon nanotube outperforms silicon
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P#s 140200US01, P150242, P170130 and P210216 for aligned CNTs and P150061, P170037 and P180065 for related processes